1. Field of the Invention
The present invention generally relates to a semiconductor device. It particularly relates to a semiconductor device including a bipolar transistor. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
For micro-fabrication and high performance of bipolar transistors, a technique is commonly used in which polysilicon is used for a base lead-out electrode and the diffusion layers for the base and emitter are determined by self-alignment ("polysilicon self-alignment technique").
FIG. 27 is a cross sectional view of a conventional BiCMOS for using the technique mentioned above, in which NPN bipolar, NMOS and PMOS transistors are mounted on the same integrated circuit.
FIG. 28 is a plan view of a portion of the NPN bipolar transistor shown in FIG. 27. FIG. 29 is an enlarged view of a portion of the NPN bipolar transistor shown in FIG. 27.
A manufacturing process of the BiCMOS shown in FIG. 7 and the configuration thereof will now be described in detail.
Referring to FIG. 30, an N type buried layer 2 into which antimony, arsenic or the like is injected and a P type buried layer 3 into which boron or the like is injected are formed in order on surfaces of a P.sup.- type substrate 1. Then, referring to FIG. 31, an N type epitaxial growth layer 4 is deposited on semiconductor substrate 1. When the N type epitaxial growth layer 4 is deposited, the impurities in N type buried layer 2 and P type buried layer 3 diffuse into epitaxial growth layer 4.
Referring to FIG. 32, a thermal oxide film 5 is formed on epitaxial growth layer 4. Impurity ions are injected via thermal oxide film 5 to form a P type diffusion layer 6 which serves as both a P type well of the NMOS transistor and a P type isolation of the NPN bipolar transistor.
Referring to FIG. 33, a pattern 7 of nitride film for forming a film oxide film is formed on thermal oxide film 5. Then a P type impurity is injected to form a channel cut layer 8.
Referring to FIG. 33 and 34, a field oxide film 9 is formed by thermal oxidation. Then pattern 7 of nitride film is removed.
Referring to FIG. 35, a nitride film 10 is deposited. A diffusion window 11 for forming an N type diffusion layer 12 for a collector is opened in nitride film 10. Using nitride film 10 as a mask, an N type impurity such as phosphorus is introduced through gas diffusion via diffusion window 11 to form N type diffusion layer 12.
Referring to FIG. 36, a nitride film 10 on the region in which an NPN bipolar transistor is to be formed is removed and then the oxide film 5 lying on the base region is removed to expose a surface 14 of epitaxial growth layer 4. A polysilicon layer 15 to which no impurity is added, and then a CVD oxide film 16 are deposited and then patterned so that they remain at the base region. A CVD oxide film is deposited on a surface of the semiconductor substrate and the entire surface of the CVD oxide film is anisotropically etched to form a sidewall spacer 17 at a periphery of polysilicon layer 15. The remaining nitride film 10 and thermal oxide film 5 are removed. When the films 10 and 5 are removed, the thicknesses of CVD oxide films 16 and 17 and thermal oxide film 13 are reduced.
Then gate oxidation is performed to form thermal oxide films 18 and 19 on surfaces of epitaxial growth layer 4 and P well 6. A polysilicon layer 21 to which an N type impurity such as phosphorus is added, and then a metal film 22 of MoSi, WSi or the like are deposited and patterned into a shape of a gate electrode of a MOS transistor. In the patterning (etching) of the films, the thickness of the CVD oxide film 20 lying on polysilicon layer 15 is reduced. An N type impurity such as phosphorus is ion-implanted using photoresist (not shown) as a mask to form an N type source/drain region 23 for an NMOS transistor.
Referring to FIG. 38, after a CVD oxide film is deposited, its entire surface is anisotropically etched to form a sidewall spacer 24. When the entire surface of the CVD oxide film is anisotropically etched, thermal oxide films 18, 19 and 20 are removed. An N type impurity such as arsenic is ion-implanted using photoresist as a mask, to form an N.sup.+ source/drain region 25 for an NMOS transistor.
Referring to FIG. 39, sacrificial oxidation is performed to form oxide films 26, 27 and 28. Photoresist is used as a mask and a p type impurity such as boron is ion-implanted into polysilicon layer 15 for an external base and into a PMOS region to form a P.sup.+ source/drain region 29 and an external base layer 30. The junction depth of external base layer 30 is smaller than that of P.sup.+ source/drain region 29 due to the ion-implantation via polysilicon layer 15.
Referring to FIG. 40, a CVD oxide film 31 is deposited and etched to expose an intrinsic base region 32. When polysilicon layer 15 is overetched, a surface of epitaxial growth layer 4 is scraped and a step 33 results. A P type impurity such as boron, BF.sub.2 or the like is ion-implanted to form an intrinsic base layer 34.
Referring to FIG. 41, a CVD oxide film 35 is deposited and then its entire surface is etched to form a sidewall spacer 35 at an internal wall of polysilicon layer 15 for the external base. When the entire surface of CVD oxide film 35 is etched, a surface of epitaxial growth layer 4 is scraped off by overetching and a step 36 results.
Referring to FIG. 42, a polysilicon layer 37 is deposited and an N type impurity such as arsenic is ion-implanted into layer 37. Then polysilicon layer 37 is patterned as shown in the figure so that it covers an emitter region. Then, a CVD oxide film 39 is deposited and is subject to heat treatment to form an emitter layer 38. An opening 40 is formed in CVD oxide film 39 to form a contact.
Referring to FIG. 43, metal is deposited filing opening 40 (FIG. 42) so that it is in contact with polysilicon layer 37 and the metal is patterned to form a metal interconnection 41.
A conventional BiCMOS thus configured has the problem described below.
That is, referring to FIG. 29, external base layer 30 is formed by diffusing boron from polysilicon layer 15 for the external base into epitaxial growth layer 4 for the purpose of reducing the depth of junction with epitaxial growth layer 4. Thus, external base layer 30 has the junction depth reduced at an edge of field oxide film 9. This is because the diffusion of boron is suppressed due to a portion referred to as a bird's beak (the circled portion in FIG. 29) at the edge of field oxide film 9. When reverse bias is applied to a collector and a base of an NPN bipolar transistor with junction depth reduced at an edge of a field oxide film, electric field concentration is caused at the circled portion and hence the breakdown voltage between the collector and the base is lowered, since the radius of curvature of the PN junction at this portion is small.